In general, semiconductor materials may be processed in semiconductor technology on or in a substrate (also referred to as a wafer or a carrier), e.g. to fabricate integrated circuits (also referred to as chips). During processing the semiconductor material, certain process steps may be applied, such as thinning the wafer, doping a semiconductor material, or forming one or more layers over the wafer.
Conventionally, the wafer is thinned to remove excess material from the backside of the integrated circuits until the integrated circuits have a predefined thickness, which influences their electronic efficiency. For a precise thinning of all integrated circuits to the same thickness, the integrated circuits may need to be aligned parallel to a thinning plane. To align the integrated circuits, the wafer may be incorporated into a planarization package, which is planarized to provide two almost plane-parallel surfaces, which enable a precise thinning of all integrated circuits of the wafer.
For minimizing a deviation of the two almost plane-parallel surfaces, the chuck on which the planarization package is disposed during planarization may be adjusted to the plane in which the planarization package is planarized. During this process, the chuck may be aligned plane-parallel to the planarization plane by a self-planarization process.
Conventionally, the self-planarization process is limited in its preciseness due to inherent technological variations of the process itself. Therefore, the almost plane-parallel surfaces of the planarization package may deviate from each other up to the maximum preciseness of the self-planarization process. Minimizing variations in the resulting thickness of the integrated circuits (also referred to as total thickness variation) may thus be limited, e.g. to more than about 2 μm in case of a 300 mm wafer diameter. The total thickness variation may not be accessible for subsequent corrections, and may be transferred into further process steps. By way of example, a stability of the total thickness variation for the readily fabricated chips may be limited to about ±3 μm, e.g., measured across a plurality of processed wafers or a plurality of processed chips in a wafer.